Plan B: AN231E04 FPAA

The Anadigm AN231E04 field-programmable analog array is the closest modern equivalent to the CY8C29466’s reconfigurable analog fabric. If Phase 1 reveals that the PSoC 1’s switched-capacitor blocks have intolerable clock noise, reconfiguration glitches, or insufficient bandwidth for musical self-oscillation, the AN231E04 is the fallback.

This page documents the comparison, the migration path, and the decision criteria.

Why AN231E04

The AN231E04 is a purpose-built reconfigurable analog signal processor. It shares the same switched-capacitor foundation as the CY8C29466 but with better analog performance across every measurable axis:

Parameter	CY8C29466 (Plan A)	AN231E04 (Plan B)
Configurable analog blocks	12 (4 CT + 8 SC)	4 CABs with 8 op-amps, 4 comparators, 4 I/O op-amps
Signal bandwidth	Audio-range SC	DC to 999 kHz general, up to 2 MHz
Internal sample rate	Low MHz range	Up to 16 MHz
Op-amp GBW	Not specified (general purpose)	18 MHz
Input offset	~4 mV typical CMOS	Under 250 μV (chopper-stabilized)
Reconfiguration	Sequential register writes (~100–200 ns each)	Shadow memory — single clock cycle swap
Onboard CPU	M8C @ 24 MHz	None
Interface	I2C slave	SPI (raw config data)
Supply	3.0–5.25 V	3.3 V
Package	48-pin SSOP	44-pin QFN (7×7 mm)
Status	Discontinued	Active — Okika Devices acquired Anadigm (April 2025)
Toolchain	PSoC Designer (legacy, Windows)	AnadigmDesigner2 + open-source Python (pikapy)

The AN231E04’s higher SC clock rate (16 MHz internal) pushes clock noise products further above the audio band. Its chopper-stabilized amplifiers produce lower DC offset. And its shadow reconfiguration memory solves the mid-note topology switching challenge — load a new configuration in the background, then swap atomically without any intermediate states hitting the analog output.

What the FPAA Lacks

No onboard CPU. The AN231E04 is purely analog — every configuration change must be pushed by an external microcontroller over SPI. In Timbre’s Plan A architecture, each CY8C29466 handles its own I2C protocol, interprets parameter packets, and manages reconfiguration timing locally. With the FPAA, all that intelligence moves to the ESP32 master controller.

This shifts the system architecture:

graph LR
    subgraph "Plan A — PSoC 1"
        ESP_A["ESP32"] -->|"I2C: set cutoff 2kHz"| PSoC["CY8C29466<br/>interprets + reconfigures"]
    end

    subgraph "Plan B — FPAA"
        ESP_B["ESP32"] -->|"SPI: full config bitstream"| FPAA["AN231E04<br/>loads blindly"]
    end

    style PSoC fill:#134e4a,stroke:#0d9488,color:#ccfbf1
    style FPAA fill:#1a3a37,stroke:#0d9488,color:#ccfbf1

Plan A: the voice chip is a smart peripheral. Plan B: the voice chip is a dumb fabric that the controller programs entirely.

No digital blocks. The CY8C29466 has 16 digital blocks (timers, counters, PWM, UART, SPI) that can complement the analog path — generating clocks, measuring frequencies, implementing digital logic alongside the analog processing. The AN231E04 has a LUT (8×256-bit lookup table for waveform synthesis and nonlinear functions) but no general-purpose digital logic.

Fewer GPIO. The CY8C29466 has 44 GPIO pins. The AN231E04 has 7 analog I/Os and an SPI port.

Hardware Options

Okika Pika Board (Development)

The OTC2310K04-PIKA is a Raspberry Pi HAT with 4 AN231E04 chips, onboard chip-to-chip routing, and 8 input anti-alias filters. At $156 it’s a ready-made 4-voice development platform.

16 total CABs across 4 chips
Switchable chip-to-chip interconnects (no jumpers needed)
16 MHz master clock with external clock input
SPI interface to Pi or any MCU
Stackable for expansion

A Pika board driven by an ESP32-S3 (instead of a Pi) could serve as a Plan B prototype without designing a custom PCB.

Bare Chips (Production)

The AN231E04 is available from Okika Devices in volume:

Quantity	Approx. Unit Cost
1	~$15
10-pack	~$12/ea
260 (tray)	~$8.50/ea
1000 (reel)	~$7.50/ea

A 16-voice system would need 16 chips — roughly $120–240 in silicon depending on volume, plus PCB design.

Migration Path

The critical insight: Timbre’s system architecture transfers almost entirely. The ESP32 master controller, MIDI/MPE parsing, voice allocation, envelope generation, modulation routing — none of that changes. The voice chip is a black box that accepts parameters and produces audio. Swapping the black box means:

Replace I2C with SPI — the bus protocol changes, but the ESP32 supports both natively. SPI is actually faster for bulk configuration transfers.
Move parameter → register translation to the ESP32 — instead of the voice chip interpreting “set cutoff to 2kHz,” the ESP32 pre-computes the full AN231E04 configuration bitstream. This is more work for the controller but the ESP32-S3’s dual cores have plenty of headroom.
Pre-compute configuration snapshots — AnadigmDesigner2 exports configuration data for each desired topology. Store these as firmware constants (just like the PSoC register snapshots in Plan A). Interpolating between configurations for continuous parameter sweeps requires computing partial configs — the pikapy Python library may help prototype this.
Redesign voice board PCB — different chip, different footprint, different power requirements. But the board-level architecture (chips on a bus, audio summing, expansion connector) stays the same.

Decision Criteria

Switch to Plan B if Phase 1 characterization reveals any of the following:

Condition	Threshold
SC clock noise in audio band	>−60 dB relative to fundamental after output filtering
Reconfiguration transients	Audible clicks/pops during mid-note topology switching that resist mitigation
Pitch tracking nonlinearity	>50 cents deviation from equal temperament across 4 octaves
Self-oscillation instability	Cannot maintain stable oscillation across the audible range

If the CY8C29466 passes Phase 1, Plan A continues — the inventory advantage, per-voice CPU, and simpler system architecture make it the better choice when the analog performance is sufficient.

If it fails on any of the above, the AN231E04 is ready. The Pika board can be ordered immediately for prototyping while a custom voice board is designed.