CY8C29466 Reference

The CY8C29466-24PXI is the top-tier variant of the Cypress PSoC 1 family. It was designed as a “programmable system-on-chip” for mixed-signal applications — sensor conditioning, motor control, touch sensing — but its dynamically reconfigurable analog fabric makes it uniquely suited as a per-voice analog synthesizer engine.

Key Specifications

Parameter	Value
CPU	M8C @ 24 MHz (8-bit Harvard architecture)
Flash	32 KB
SRAM	2 KB
Analog blocks	12 (4 columns × 3 rows)
Digital blocks	16 (4 columns × 4 rows)
ADC resolution	Up to 14-bit (using analog blocks)
DAC resolution	Up to 9-bit (using analog blocks)
GPIO	Up to 44 pins (48-pin SSOP package)
I2C	Hardware slave, firmware-defined address
Supply voltage	3.0V – 5.25V
Package	48-pin SSOP
Status	Discontinued (Cypress → Infineon)

From Sensor Platform to Synthesis Engine

The CY8C29466 was designed for sensor conditioning, motor control, and touch sensing — not audio. Its datasheet talks about ADC front-ends and capacitive sensing, not oscillators and filters. But there is a deeper lineage connecting this chip to analog synthesis, and it runs through the most celebrated synth ICs ever made.

Hans Camenzind designed the 555 timer in 1971 for Signetics — an analog IC so versatile it has appeared in virtually every category of electronic product. But Camenzind’s broader ambition was configurable analog silicon: his “Monochip” at Interdesign allowed customers to define analog functions through mask programming, a precursor to the field-programmable concept. When Ferranti acquired Interdesign in 1977, the configurable-analog expertise dispersed. Doug Curtis, working in this same intellectual tradition, founded Curtis Electromusic and produced the CEM3340 VCO, CEM3320 VCF, and their descendants — the chips inside the Prophet-5, OB-Xa, Jupiter-6, and Memorymoog. The most iconic analog synthesizer sounds in history descend from the configurable-analog lineage that Camenzind’s work helped establish.

Cypress Semiconductor’s PSoC family brought that same concept — configurable analog blocks on a single die — to commodity microcontroller pricing. At three to nine dollars per chip, a CY8C29466 provides twelve reconfigurable analog blocks and their own control processor for a fraction of what a discrete CEM3340 + CEM3320 + envelope generator build costs (typically twenty-five to sixty dollars in equivalent components). The PSoC returns configurable analog to its musical roots, sixty years after the modular synthesizer first proved that flexible analog topology is musically powerful. The Lineage page traces this full arc.

Analog Block Architecture

The 12 analog blocks are organized in a 4×3 grid. Each column has one Type C (continuous-time) block and two Type SC (switched-capacitor) blocks:

Column 0    Column 1    Column 2    Column 3
┌────────┐ ┌────────┐ ┌────────┐ ┌────────┐
│ ACB00  │ │ ACB01  │ │ ACB02  │ │ ACB03  │  ← Type C (continuous-time)
│  (CT)  │ │  (CT)  │ │  (CT)  │ │  (CT)  │
├────────┤ ├────────┤ ├────────┤ ├────────┤
│ ASB10  │ │ ASB11  │ │ ASB12  │ │ ASB13  │  ← Type SC (switched-cap)
│  (SC)  │ │  (SC)  │ │  (SC)  │ │  (SC)  │
├────────┤ ├────────┤ ├────────┤ ├────────┤
│ ASB20  │ │ ASB21  │ │ ASB22  │ │ ASB23  │  ← Type SC (switched-cap)
│  (SC)  │ │  (SC)  │ │  (SC)  │ │  (SC)  │
└────────┘ └────────┘ └────────┘ └────────┘

Type C Blocks (Continuous-Time)

The four Type C blocks can be configured as:

• Comparators (with programmable threshold)
• Continuous-time amplifiers (gain stages)
• DAC output buffers

These are used in Timbre for comparator functions in relaxation oscillators and as output buffers.

Type SC Blocks (Switched-Capacitor)

The eight Type SC blocks are the core of Timbre’s voice engine. Each can be configured as:

• Integrator (for filter stages)
• Sample-and-hold
• Inverting/non-inverting amplifier
• First-order filter section

Two SC blocks chained form a biquad section (second-order filter). Three form a sixth-order filter. The routing between blocks is programmable via the analog interconnect matrix.

Switched-Capacitor Clock

SC blocks are clocked by one of several internal clock sources derived from the system clock. The SC clock frequency determines the filter’s characteristic frequency:

f_center = f_clock × (C_ratio)

where C_ratio is set by the capacitor configuration registers. Changing the clock divider or the capacitor ratio changes the filter’s center/cutoff frequency — this is how “voltage-controlled filter” behavior is achieved under digital control.

The SC clock typically runs at 100kHz–2MHz. For audio-frequency self-oscillation, the clock must be high enough that the filter’s center frequency falls in the audible range (20Hz–20kHz) while keeping clock noise products above the audible band.

Dynamic Reconfiguration

The analog block configuration registers can be written by the M8C core at any time during operation. A register write takes 2–4 CPU cycles (~100–200ns at 24MHz). This enables:

• Changing filter topology mid-note (LP → BP → HP)
• Switching between oscillation modes
• Rerouting the analog signal path
• Adjusting Q/resonance, gain, and offset in real time

The reconfiguration is not glitch-free in all cases — switching the capacitor network of an SC block can produce a transient. Phase 1 characterization will determine which transitions produce audible artifacts and which are clean enough for mid-note use.

For the full treatment of reconfiguration tiers and the operating models they enable, see Reconfiguration.

I2C Slave

The CY8C29466 implements an I2C slave using its digital blocks. The slave address is configurable in firmware (7-bit address, up to 127 devices per bus). The I2C module supports:

• Standard mode (100kHz) and Fast mode (400kHz)
• Multi-byte read/write transactions
• Clock stretching (the PSoC can hold SCL low while processing a received byte)

In Timbre’s architecture, the ESP32 master writes parameter packets to each voice chip. A typical packet contains:

• Filter cutoff (SC clock divider value, 2 bytes)
• Resonance / Q (capacitor ratio, 1 byte)
• VCA gain (1 byte)
• Oscillation mode (topology selector, 1 byte)
• Envelope level (1 byte)

Relevant Application Notes

App Note	Title	Relevance
AN2094	PSoC 1 — Understanding Switched Capacitor Analog Blocks	Core reference for SC filter design and clock frequency selection
AN2219	PSoC 1 — Analog Block Chaining	How to cascade SC blocks for higher-order filters; essential for biquad self-oscillation
AN2041	PSoC 1 — I2C Slave	I2C slave firmware implementation
AN2100	PSoC 1 — DAC	DAC configuration for output buffering

Academic Parallels

The closest academic work to Timbre’s approach comes from Georgia Tech, where Dr. Jennifer Hasler’s group mapped Moog transistor ladder VCFs onto floating-gate Field-Programmable Analog Arrays. Their key finding: a single FPAA could support up to twelve VCFs — a striking numerical parallel to Timbre’s twelve SC blocks per voice. The FPAA research demonstrated that reconfigurable analog synthesis is viable at the academic level and produced measurements that inform expectations for PSoC-based approaches.

The fundamental difference is in the analog domain. Hasler’s FPAAs use continuous-time floating-gate transistor arrays — OTA-based, current-mode circuits that preserve the continuous-time character of traditional analog synthesis. The PSoC’s SC blocks are discrete-time and clocked, producing a fundamentally different sonic character. The FPAA approach offers better fidelity to traditional analog but requires slower programming (floating-gate tunneling) and is more susceptible to temperature drift. The SC approach sacrifices continuous-time operation for deterministic, near-instantaneous reconfiguration via register writes. The Plan B: FPAA page evaluates the Anadigm AN231E04 as a potential alternative platform, comparing its trade-offs directly against the PSoC approach.

PSoC Designer Toolchain

Firmware development uses PSoC Designer, the legacy Cypress IDE. It runs on Windows (or Wine on Linux with some effort). The toolchain includes:

• Graphical analog block configuration (drag-and-drop block placement and routing)
• Auto-generated C API for each configured block
• ImageCraft C compiler (included) or GCC (with configuration)
• Programmer support for MiniProg1/3

The graphical block configuration tool is the key productivity advantage — it generates the register initialization code for analog block configurations, eliminating manual register-level programming for topology changes.

For runtime reconfiguration (Timbre’s core feature), the generated register values are captured and stored as firmware constants. Switching between topologies at runtime is a sequence of register writes using these pre-computed values.